AnDAPT is fabless power semiconductor company revolutionizing power management through software-defined solutions offering unprecedented programmability to create and customize a power management IC (PMIC) within minutes. These solutions shorten time-to-market and afford flexibility for rapid changes keeping pace with user-defined requirements.
AnDAPT is revolutionizing the power management market with its disruptive Software Defined Power Solution, offering customers unprecedented programmability to create and customize a Power Management IC (PMIC) within minutes. AnDAPT power solutions target markets where the number of power rails is large, therefore require power management functions, but volume is not large enough to justify development of a full custom PMIC.
As a Senior FPGA Circuit Design Engineer with AnDAPT you will be responsible for the Definition, Design and Support of the hardware Platform that is used for our Software Defined Power Solution. We are currently in the process of defining and designing our second-generation platform. You will work directly with the Design Team in San Jose. We are looking for candidates that can design (sub)blocks without supervision and are able to work with other engineers with different backgrounds.
- Design of programmable hardware building blocks like Timers, Digital Filters, Look-Up Tables & Serial Data Interfaces.
- Design of Digital Fabric.
- Test & Verification of Digital Fabric and Hardware.
- Assist the Layout Team with Mask Design.
- Silicon Verification.
- Assisting the Systems and Software Team with trouble shooting.
- Automated evaluation of hardware building blocks using Python.
- MSc in Electronic Engineering or equivalent.
- Familiarity with FPGA Design Methodology and Custom Design Techniques.
- Understanding of power conversion topologies (buck, boost, buck-boost, LDO, Load-Switches etc).
- Experience with all aspects of IC Design (Simulation/Mask Design/Manufacturing etc).
- Fluency in RTL Designs for non-custom FPGA blocks, from concept through GDS (RTL Code, Timing analysis & closure, etc.).
- 5 years experience with Digital Design.
- 3 years experience with FPGA Design.
- Hands on experience in building designs out of Cadence Design tools.
- Excellent written and oral communications with experience in specification creation, technical report writing and test plans/instructions.
- Experience with the use of standard power supply laboratory test equipment i.e. (DMM, PS, Oscilloscope, Power Meter, Amp meters, Current probes, etc.).