Cyclone V
POWER TREE MAPPING – CYCLONE V
| # | Rail | Seq | Power Component | Type | Upstream Rail | Vinput (V) | Vout (V) | Iout (A) | AnDAPT PMIC |
| 1 | VCCINT (VCCINT_FPGA, VCCEL_GXB) | 1 | C865 | 1-Ph DrMOS Ctrl | PVIN | 12 | 1.1 | 15 | ARD_A_CYCV_IC1 |
| 2 | VCCINT_HPS | 2 | C200 | Sync Buck | PVIN | 12 | 1.1 | 2.5 | ARD_A_CYCV_IC1 |
| 3 | HPS3V3 | 3 | C200 | Sync Buck | PVIN | 12 | 3.3 | 5 + 1 | ARD_A_CYCV_IC1 |
| 4 | HPS2V5 (HPS_2V5, HPS2V5FLIT) | 4 | C710 | LDO | HPS3V3 | 3.3 | 2.5 | 1 | ARD_A_CYCV_IC1 |
| 5 | VCCIO (VCCIO1V5HPS, FPGA1V5) | 5 | C200 | Sync Buck | PVIN | 12 | 1.5 | 3 | ARD_A_CYCV_IC1 |



