Low Power (Minimum Rails)

ARD_X_AUP_A1

Artix UltraScale+
Low Power (Minimum Rails)

The ARD_X_AUP_A1 and ARD_X_AUP_A2 are scalable power supplies designed to provide power to Xilinx Artix UltraScale+ Medium/Low power FPGA devices. The designs are scalable to support the cost- and power-optimized FPGA devices including AU10P, AU15P, AU20P, and AU25P.

Design recommended by AMD

LOW POWER (MINIMUM RAILS)


POWER TREE MAPPING – LOW POWER

#RailSeqPower ComponentTypeUpstream RailVinput (V)Vout (V)Iout (A)AnDAPT PMIC
1VCCINT1C150Async BuckPVIN120.726ARD_X_AUP_A1
2VBUS1C150Async BuckPVIN121.80.35 + 0.35 + 0.75ARD_X_AUP_A1
3VCCBRAM / INT_IO2C710LDOVBUS1.80.850.35ARD_X_AUP_A1
4VCCAUX / ADC3C750Load SwitchVBUS1.81.80.35ARD_X_AUP_A1
5VMGTAVTT4C150Async BuckPVIN121.23ARD_X_AUP_A1
6VMGTAVCCAUX5C750Load SwitchPVIN121.80.15ARD_X_AUP_A1
7VMGTAVCC6C710LDOVBUS1.80.90.75ARD_X_AUP_A1
8VCCO7C150Async BuckPVIN121.1 – 3.3,
1 – 1.8
1.5ARD_X_AUP_A1

ANDAPT SOLUTION – LOW POWER

THERMAL VIEW IC1


DESIGN VIEW IC1

en_US
Scroll to Top