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ARD_X_AUP_A1

Artix UltraScale+ Low Power (Minimum Rails)

The ARD_X_AUP_A1 and ARD_X_AUP_A2 are scalable power supplies designed to provide power to Xilinx Artix UltraScale+ Medium/Low power FPGA devices. The designs are scalable to support the cost- and power-optimized FPGA devices including AU10P, AU15P, AU20P, and AU25P.

 

Goto WebAmP R.D. Tool
Download Test Data

Design recommended by Xilinx/AMD

LOW POWER (MINIMUM RAILS)

Image courtesy Xilinx: 
https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

 

Power Tree Mapping - Low Power (Minimum Rails)

ANDAPT SOLUTION (1XPMIC)

DESIGN VIEW IC1 Low Power (Minimum Rails)

Test Data

Thermal View IC1 Low Power (Minimum Rails)

for more test data, click Downlod Bench Data below:

Download Design
Download Test Data
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