Low Power (Minimum Rails)

ARD_X_AUP_A1

Artix UltraScale+
Low Power (Minimum Rails)

The ARD_X_AUP_A1 and ARD_X_AUP_A2 are scalable power supplies designed to provide power to Xilinx Artix UltraScale+ Medium/Low power FPGA devices. The designs are scalable to support the cost- and power-optimized FPGA devices including AU10P, AU15P, AU20P, and AU25P.

WebAmP R.D. Tool

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Design recommended by AMD

LOW POWER (MINIMUM RAILS)

POWER TREE MAPPING – LOW POWER

#	Rail	Seq	Power Component	Type	Upstream Rail	Vinput (V)	Vout (V)	Iout (A)	AnDAPT PMIC
1	VCCINT	1	C150	Async Buck	PVIN	12	0.72	6	ARD_X_AUP_A1
2	VBUS	1	C150	Async Buck	PVIN	12	1.8	0.35 + 0.35 + 0.75	ARD_X_AUP_A1
3	VCCBRAM / INT_IO	2	C710	LDO	VBUS	1.8	0.85	0.35	ARD_X_AUP_A1
4	VCCAUX / ADC	3	C750	Load Switch	VBUS	1.8	1.8	0.35	ARD_X_AUP_A1
5	VMGTAVTT	4	C150	Async Buck	PVIN	12	1.2	3	ARD_X_AUP_A1
6	VMGTAVCCAUX	5	C750	Load Switch	PVIN	12	1.8	0.15	ARD_X_AUP_A1
7	VMGTAVCC	6	C710	LDO	VBUS	1.8	0.9	0.75	ARD_X_AUP_A1
8	VCCO	7	C150	Async Buck	PVIN	12	1.1 – 3.3, 1 – 1.8	1.5	ARD_X_AUP_A1

ANDAPT SOLUTION – LOW POWER

THERMAL VIEW IC1

DESIGN VIEW IC1

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