Medium Power

ARD_X_AUP_A2

Artix UltraScale+ Medium Power

The ARD_X_AUP_A1 and ARD_X_AUP_A2 are scalable power supplies designed to provide power to Xilinx Artix UltraScale+ Medium/Low power FPGA devices. The designs are scalable to support the cost- and power-optimized FPGA devices including AU10P, AU15P, AU20P, and AU25P.

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Design recommended by AMD Xilinx

MEDIUM POWER

POWER TREE MAPPING – MEDIUM POWER

#	Rail	Seq	Power Component	Type	Upstream Rail	Vinput (V)	Vout (V)	Iout (A)	AnDAPT PMIC
1	VCCINT, BRAM, VCCINT_IO	1	C150	Async Buck	PVIN	12	0.72 / 0.85	1.2	ARD_X_AUP_A2
2	VCCAUX, VCCAUXIO, VCCADC	2	C710	LDO	VBUS	2	1.8	0.35	ARD_X_AUP_A2
3	VBUS	1	C150	Async Buck	PVIN	12	2	0.35 + 0.15	ARD_X_AUP_A2
4	VMGAVTT	3	C200	Sync Buck	PVIN	12	1.2	3 + 0.75	ARD_X_AUP_A2
5	VMGTAVCCAUX	4	C710	LDO	VBUS	2	1.8	0.15	ARD_X_AUP_A2
6	VMGTYAVCC	5	C710	LDO	VMGAVTT	1.2	0.9	0.75	ARD_X_AUP_A2
7	VCCO	6	C150	Async Buck	PVIN	12	1 – 3.3	1.5	ARD_X_AUP_A2

ANDAPT SOLUTION – MEDIUM POWER

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