Medium/Low Power

ARD_X_AX7_A1

Artix-7
(Medium/Low Power)

The ARD_X_AX7_A1 is a scalable power supply designed to provide power to Xilinx Artix-7 Medium/Low power FPGA devices. The design is scalable to support the cost-sensitive transceiver optimized devices including XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, and XC7A75T.

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MEDIUM/LOW POWER

POWER TREE MAPPING – MEDIUM/LOW POWER

#	Rail	Seq	Power Component	Type	Upstream Rail	Vinput (V)	Vout (V)	Iout (A)	AnDAPT PMIC
1	VCCINT, VCCBRAM, MGTAVCC	1	C200	Sync Buck	V_IN	12	0.95 / 1	5.2	ARD_X_AX7_A1_IC1
2	VCC_DDR	4	C200	Sync Buck	V_IN	1.8	1.35 to 1.5	<2	ARD_X_AX7_A1_IC1
3	VMGTAVTT	4	C200	Sync Buck	V_IN	12	1.2	≤1	ARD_X_AX7_A1_IC1
4	VCCAUX, VCCADC	2	C150	Async Buck	V_IN	12	1.8	<0.31	ARD_X_AX7_A1_IC1
5	VCC_IO	4	C710	SIM LDO	V_IN	12	1.8 or 3.3	<0.2	ARD_X_AX7_A1_IC1
6	VCCO [0.1…]	3	CLDO	Corner LDO	V_IN	12	1.2 or 3.3	≤0.03	ARD_X_AX7_A1_IC1

ANDAPT SOLUTION

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