Full Power Management

ARD_X_VRX_A2

Virtex UltraScale+
(Full Power Management)

The ARD_X_VRX_A1 and ARD_X_VRX_A2 are scalable power supplies designed to provide power to Xilinx Virtex UltraScale+ FPGA devices. The designs are scalable to support the Full Power Management FPGA devices.

WebAmP R.D. Tool

Download Test Data

Design recommended by AMD

FULL POWER MANAGEMENT

ARD_X_VRX_A2 Power Tree

POWER TREE MAPPING – FULL POWER MANAGEMENT

#	Rail	Sheet Column	Seq	Power Component	Type	Upstream Rail	Vinput (V)	Vout (V)	Iout (A)	AnDAPT PMIC
1	VCCINT	12	1	C870	2-ph DrMOS Ctrl	PVIN	12	0.72	60	ARD_X_VRX_A2_IC1
2	VCCBRAM (VCCINT_IO, VCCBRAM)	3	2	C200	Sync Buck	PVIN	12	0.9	6	ARD_X_VRX_A2_IC1
3	VCCAUX (VCCAUX, VCCAUX_IO, VCCADC)	1	3	C200	Sync Buck	PVIN	12	1.8	3	ARD_X_VRX_A2_IC1
4	VMGTAVTT	7	4	C200	Sync Buck	PVIN	12	1.2	6	ARD_X_VRX_A2_IC1
5	VMGTAVCCAUX	2	5	C200	Sync Buck	PVIN	12	1.8	0.5	ARD_X_VRX_A2_IC2
6	VMGTAVCC	3	6	C200	Sync Buck	PVIN	12	0.9	6	ARD_X_VRX_A2_IC2
7	VCC_HBM (VCC_HBM, VCC_IO_HBM)	10	7	C865	1-ph DrMOS Ctrl	PVIN	12	1.2	15	ARD_X_VRX_A2_IC2
8	VCCAUX_HBM	4	8	C200	Sync Buck	PVIN	12	2.5	0.6	ARD_X_VRX_A2_IC2
9	VCCO_HDIO	5	9	C200	Sync Buck	PVIN	12	3.3	3	ARD_X_VRX_A2_IC3
10	VCCO_HPIO	6	10	C200	Sync Buck	PVIN	12	1.8	3	ARD_X_VRX_A2_IC3
11	VCC_DDR	7	11	C200	Sync Buck	PVIN	12	1.2	4	ARD_X_VRX_A2_IC3
12	DDR_VTT (DDR_VTT, DRR_VREF)	8	12	C210	VTT Terminator	VCC_DDR	1.2	0.6	4	ARD_X_VRX_A2_IC3

ANDAPT SOLUTION – FULL POWER MANAGEMENT

ARD_X_VRX_A2 Andapt Solution

DESIGN VIEW IC1

THERMAL VIEW IC1

DESIGN VIEW IC2

ARD_X_VRX_A2_IC2 design view

THERMAL VIEW IC2

ARD_X_VRX_A2_IC2 thermal view

DESIGN VIEW IC3

THERMAL VIEW IC3

Download Design

Download Test Data

WebAmP R.D. Tool