Minimum Rails

ARD_X_VRX_A1

Virtex UltraScale+
(Minimum Rails)

The ARD_X_VRX_A1 is a scalable power supply designed to provide power to Xilinx Virtex UltraScale+ FPGA devices. The designs is scalable to support the cost- and power-optimized FPGA devices.

Design recommended by AMD

MINIMUM RAILS


POWER TREE MAPPING – MINIMUM RAILS

#RailSeqPower ComponentTypeUpstream RailVinput (V)Vout (V)Iout (A)AnDAPT PMIC
1VCCINT
(VCCINT, VCCINT_IO, VCCBRAM)
1C8702-ph DrMOS CtrlPVIN120.8560ARD_X_VRX_A1_IC1
2VCCAUX
(VCCAUX, VCCAUX_IO, VCCADC)
2C200Sync BuckPVIN121.83ARD_X_VRX_A1_IC1
3VMGTAVTT3C200Sync BuckPVIN121.24ARD_X_VRX_A1_IC1
4VMGTAVCCAUX4C200Sync BuckPVIN121.80.5ARD_X_VRX_A1_IC1
5VMGTAVCC5C200Sync BuckPVIN120.96ARD_X_VRX_A1_IC2
6VCCO_HDIO
(VCCO_HDIO, VCCO_HPIO)
6C200Sync BuckPVIN121.83ARD_X_VRX_A1_IC2
7VCC_DDR6C200Sync BuckPVIN121.24ARD_X_VRX_A1_IC2
8DDR_VTT (DDR_VTT, DDR_VREF)7C210VTT TerminatorVCC_DDR1.20.64ARD_X_VRX_A1_IC2

ANDAPT SOLUTION – MINIMUM RAILS


DESIGN VIEW IC1

THERMAL VIEW IC1


DESIGN VIEW IC2

THERMAL VIEW IC2

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