Always On, Cost-Optimized (Minimum Rails)
COST-OPTIMIZED WITHOUT MGT (MINIMUM RAILS)
POWER TREE MAPPING – COST-OPTIMIZED WITHOUT MGT
| # | Rail | Seq | Power Component | Type | Upstream Rail | Vinput (V) | Vout (V) | Iout (A) | AnDAPT PMIC |
| 1 | VCCINT (VCCINT, VCCBRAM, VCCINT_IO, VCC_PSINTLP, VCC_PSINTFP, VCC_PSINTFP_DDR) | 1 | C200 | Sync Buck | PVIN | 12 | 0.72 | 4.2 | ARD_X_ZUM_A1_IC1 |
| 2 | VCCAUX (VCCAUX, VCCAUX_IO, VCCADC, VCC_PSAUX, VCC_PSADC, VCC_PSDDR_PLL) | 2 | C150 | Async Buck | PVIN | 12 | 1.8 | 1 + 0.5 + 0.1 | ARD_X_ZUM_A1_IC1 |
| 3 | VCC_PSPLL | 3 | C710 | LDO | VCCAUX | 1.8 | 1.2 | 0.1 | ARD_X_ZUM_A1_IC1 |
| 4 | VCCO_PSDDR (VCCO_PSDDR, DDR_VDDQ/VDD) | 4 | C150 | Async Buck | PVIN | 1.2 | 1.2 | 3 | ARD_X_ZUM_A1_IC1 |
| 5 | VCCO_PSIO | 5 | C750 | Load Switch | VCCAUX | 1.8 | 1.8 | 0.5 | ARD_X_ZUM_A1_IC1 |
| 6 | VTT | 6 | C210 | VTT Term | VCCO_PSDDR | 1.2 | 0.6 | 1.5 | ARD_X_ZUM_A1_IC1 |
ANDAPT SOLUTION – COST-OPTIMIZED WITHOUT MGT (MINIMUM RAILS)
THERMAL VIEW IC1 COST-OPTIMIZED WITHOUT MGT (MINIMUM RAILS)
DESIGN VIEW IC1 COST-OPTIMIZED WITHOUT MGT (MINIMUM RAILS)
TEST DATA
