Always On, Cost-Optimized (Minimum Rails)

ARD_X_ZUM_A1

Zynq UltraScale+ MPSoC Always On,
Cost-Optimized (Minimum Rails)

In always on, cost-optimized applications, a significant
amount of power rail consolidation is possible.

Design recommended by AMD

COST-OPTIMIZED WITHOUT MGT (MINIMUM RAILS)


POWER TREE MAPPING – COST-OPTIMIZED WITHOUT MGT

#RailSeqPower ComponentTypeUpstream RailVinput (V)Vout (V)Iout (A)AnDAPT PMIC
1VCCINT
(VCCINT, VCCBRAM,
VCCINT_IO, VCC_PSINTLP,
VCC_PSINTFP, VCC_PSINTFP_DDR)
1C200Sync BuckPVIN120.724.2ARD_X_ZUM_A1_IC1
2VCCAUX
(VCCAUX, VCCAUX_IO,
VCCADC, VCC_PSAUX,
VCC_PSADC, VCC_PSDDR_PLL)
2C150Async BuckPVIN121.81 + 0.5 + 0.1ARD_X_ZUM_A1_IC1
3VCC_PSPLL3C710LDOVCCAUX1.81.20.1ARD_X_ZUM_A1_IC1
4VCCO_PSDDR
(VCCO_PSDDR,
DDR_VDDQ/VDD)
4C150Async BuckPVIN1.21.23ARD_X_ZUM_A1_IC1
5VCCO_PSIO5C750Load SwitchVCCAUX1.81.80.5ARD_X_ZUM_A1_IC1
6VTT6C210VTT TermVCCO_PSDDR1.20.61.5ARD_X_ZUM_A1_IC1

ANDAPT SOLUTION – MINIMUM RAILS

THERMAL VIEW IC1


DESIGN VIEW IC1


TEST DATA

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