Always On, Cost-Optimized (With MGT)

ARD_X_ZUM_A2

Zynq UltraScale+ MPSoC
(Always On, Cost-Optimized)

In always on, cost-optimized applications, a significant amount of power rail consolidation is possible.

COST-OPTIMIZED WITH MGT


POWER TREE MAPPING – COST-OPTIMIZED WITH MGT

#RailSeqPower ComponentTypeUpstream RailVinput (V)Vout (V)Iout (A)AnDAPT PMIC
1VCCINT, VCCBRAM, VCCINT_IO,
VCC_PSINTFP, VCC_PSINTLP,
VCC_PSINTFP_DDR
1C860DrMOS CtrlVIN120.8535ARD_X_ZUM_A2_IC1
2VCCO_PSDDR4C710SIM LDOVCCAUX1.81.1 – 1.50.5ARD_X_ZUM_A2_IC1
3VCCAUX, VCCAUX_IO, VCCADC, VCC_PSAUX, VCC_PSADC, VCC_PSDDR_PLL,
VCCO_HDIO, VCCO_HPIO
2C200Sync BuckVIN121.81.04 + 0.5ARD_X_ZUM_A2_IC1
4VCCO_PSIO [0:3]5C200Sync BuckVIN121.8 – 3.30.300ARD_X_ZUM_A2_IC2
5VCCINT_VCU*9C200Sync BuckVIN120.92ARD_X_ZUM_A2_IC2
6VMGTAVTT (GTH),
VMGTYAVTT (GTY), VCC_PSPLL
3C220Sync Buck HCVIN121.22.6 – 10.6ARD_X_ZUM_A2_IC2
7VPS_MGTRAVCC6CLDOCorner LDOVIN120.85/0.90.3ARD_X_ZUM_A2_IC2
8VMGTVCCAUX (GTH),
VMGTYVCCAUX (GTH),
VPS_MGTRAVTT
7C200Sync BuckVIN121.80.2ARD_X_ZUM_A2_IC2
9VMGTAVCC (GTH),
VMGTYAVCC (GTY)
8C200Sync BuckVIN1.1 – 1.50.90.5ARD_X_ZUM_A2_IC2

ANDAPT SOLUTION


DESIGN VIEW IC1

THERMAL VIEW IC1


DESIGN VIEW IC2

THERMAL VIEW IC2


TEST DATA

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