Mandatory Power

ARD_X_ZUR_A1

Zynq UltraScale+ RFSoC
Gen1, Gen2, Gen3 (Mandatory Power)

The ARD_X_ZUR_A1 is a scalable power supply designed to provide power to Xilinx Zynq UltraScale+ (ZU+) RFSoC Gen1 Gen2 Gen3 device mandatory rails. The design is scalable to support the most basic ZU21DR device in Gen1 Gen2 Gen3 family with RF data converters integrated on a hardware programmable SoC using a quad-core Arm Cortex-A53 MPCore application processor and dual-core Arm Cortex-R5 MPCore real-time processor to ZU29DR devices.

WebAmP R.D. Tool

POWER TREE MAPPING – MANDATORY POWER DOMAIN

#	Rail	Seq	Power Component	Type	Upstream Rail	Vinput (V)	Vout (V)	Iout (A)	AnDAPT PMIC
1	VCCINT	1	C870	DrMOS Ctrl 2-ph	V_IN	12	0.72 / 0.85	45	ARD_X_ZUR_A1_IC1
2	VCCBRAM, INT_IO, INT_AMS, SDFEX	2	C860	DrMOS Ctrl 1-ph	V_IN	12	0.85	28	ARD_X_ZUR_A1_IC1
3	VMGTAVTT, VCC_PSPLL, VCCU_PLL	2	C200	Sync Buck	V_IN	12	1.2	4	ARD_X_ZUR_A1_IC1
4	MGTAVCC	2	C200	Sync Buck	V_IN	12	0.9	2	ARD_X_ZUR_A1_IC1
5	VPS_MGTRAVCC	3	C710	SIM LDO	MGTAVCC	0.9	0.85	0.3	ARD_X_ZUR_A1_IC1
6	VCCO_PSDDR, DDR_VDDQ	6	C200	Sync Buck	V_IN	12	1.1 – 1.5	6	ARD_X_ZUR_A1_IC2
7	VCCAUX, ADC, IO, VCCPSAUX, DDR_PLL, ADC	5	C200	Sync Buck	V_IN	12	1.8	2 – 3	ARD_X_ZUR_A1_IC2
8	VCCO	6	C200	Sync Buck	V_IN	12	3.3 / 5	4	ARD_X_ZUR_A1_IC2
9	VPS_MGTAVTT, VMGTVAUX	4	C200	Sync Buck	V_IN	12	1.8	0.5	ARD_X_ZUR_A1_IC2

ANDAPT SOLUTION – MANDATORY POWER DOMAIN

DESIGN VIEW IC1

THERMAL VIEW IC1

DESIGN VIEW IC2

THERMAL VIEW IC2

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