Gen 1 Full Power

ARD_X_ZUR_B1

Zynq UltraScale+ RFSoC
Gen1 (Full Power)

The ARD_X_ZUR_B1 is a scalable power supply designed to provide power to all rails of Xilinx Zynq UltraScale+ (ZU+) RFSoC Gen1 devices. The design is scalable to support the most basic ZU39DR device in Gen1 family with RF data converters integrated on a hardware programmable SoC using a quad-core Arm Cortex-A53 MPCore application processor and dual-core Arm Cortex-R5 MPCore real-time processor to ZU49DR device in the Gen3 family.


POWER TREE MAPPING – FULL POWER DOMAIN

#RailSeqPower ComponentTypeUpstream RailVinput (V)Vout (V)Iout (A)AnDAPT PMIC
1VCCINT1C870DrMOS Ctrl 2-phVIN120.72 / 0.8545ARD_X_ZUR_B1_IC1
2VCCBRAM, INT_IO,
INT_AMS, SDFEX
2C860DrMOS Ctrl 2-phVIN120.8528ARD_X_ZUR_B1_IC1
3VMGTAVTT, VCC_PSPLL,
VCCU_PLL
2C200Sync BuckVIN121.24ARD_X_ZUR_B1_IC1
4MGTAVCC2C200Sync BuckVIN120.92ARD_X_ZUR_B1_IC1
5VPS_MGTRAVCC3C710SIM LDOMGTAVCC0.90.850.3ARD_X_ZUR_B1_IC1
6VCCO_PSDDR, DDR_VDDQ6C200Sync BuckVIN121.1 – 1.56ARD_X_ZUR_B1_IC2
7VCCAUX, ADC, IO,
VCCPSAUX, DDR_PLL, ADC
5C200Sync BuckVIN121.82 – 3ARD_X_ZUR_B1_IC2
8VCCO6C200Sync BuckVIN123.3 / 54ARD_X_ZUR_B1_IC2
9VPS_MGTAVTT, VMGTVAUX4C200Sync BuckVIN121.80.5ARD_X_ZUR_B1_IC2
10ADC_AVCC8C200Sync BuckVIN120.925/0.983.2ARD_X_ZUR_B1_IC3
11DAC_AVCC9C200Sync BuckVIN120.9256ARD_X_ZUR_B1_IC3
12ADC_AVCCAUX7C150Async BuckVIN121.81.5ARD_X_ZUR_B1_IC3
13DAC_AVCCAUX11C710SIM LDODAC_AVTT2.51.80.72ARD_X_ZUR_B1_IC3
14DAC_AVTT10C200Sync BuckVIN122.5 / 3.30.9ARD_X_ZUR_B1_IC3
ARD_X_ZUR_B1_IC3 is optional for Gen 1, Gen 2 and Gen 3.

ANDAPT SOLUTION – FULL POWER DOMAIN


DESIGN VIEW IC1 – MANDATORY

THERMAL VIEW IC1 – MANDATORY


DESIGN VIEW IC2 – MANDATORY

THERMAL VIEW IC2 – MANDATORY


DESIGN VIEW IC3 – OPTIONAL

THERMAL VIEW IC3 – OPTIONAL

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