Kintex UltraScale+

ARD_X_KUP_A

Kintex UltraScale+ (Min Rails)

The ARD_X_KUP_A is a scalable power supply designed to provide power to Xilinx Kintex UltraScale+ devices. The design is scalable and flexible to support the FPGA family SKUs from the most basic XCKU3P to the most feature-rich and power hungry XQKU15P. The programmable system integration, upward scalability, high performance/watt numbers and reduced time-to-market features of the AnDAPT’s AmP PMIC makes it an ideal match for handling power management responsibilities of Kintex UltraScale+ FPGA solutions.

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Design recommended by AMD

MIN RAILS

POWER TREE MAPPING – MIN RAILS

#	Rail	Seq	Power Component	Type	Upstream Rail	Vinput (V)	Vout (V)	Iout (A)	AnDAPT PMIC
1	VCCINT (VCCINT, VCCINT_IO, VCCBRAM)	1	C860	1-ph DrMOS Ctrl	PVIN	12	0.85	30	ARD_X_KUP_A_IC1
2	VCCAUX (VCCAUX, VCCAUX_IO, VCCADC)	2	C200	Sync Buck	PVIN	12	1.8	2	ARD_X_KUP_A_IC1
3	VMGTAVTT	3	C200	Sync Buck	PVIN	12	1.2	4	ARD_X_KUP_A_IC1
4	VMGTAVCCAUX	4	C200	Sync Buck	PVIN	12	1.8	0.1	ARD_X_KUP_A_IC1
5	VMGTAVCC	5	C200	Sync Buck	PVIN	12	0.9	4	ARD_X_KUP_A_IC2
6	VCCO_HDIO (VCCO_HDIO, VCCO_HPIO)	6	C200	Sync Buck	PVIN	12	3.3	6	ARD_X_KUP_A_IC2
7	VCC_DDR	7	C200	Sync Buck	PVIN	12	1.2	4	ARD_X_KUP_A_IC2
8	DDR_VTT	8	C210	VTT Terminator	VCC_DDR	1.2	0.6	2	ARD_X_KUP_A_IC2

ANDAPT SOLUTION – MIN RAILS

DESIGN VIEW IC1

THERMAL VIEW IC1

DESIGN VIEW IC2

THERMAL VIEW IC2

TEST DATA

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WebAmP R.D. Tool