Full Power Management

ARD_X_ZUM_D1

Zynq UltraScale+ MPSoC
(Full Power Management)

The ARD_X_ZUM_D1 is a scalable power supply designed to provide power to Xilinx Zynq UltraScale+ (ZU+) MPSoC Full Power Domain FPGAs. The design is scalable to support the most basic ZU2CG device with a dual-core Arm Cortex-53 application processor and dual-core Arm Cortex-R5F real-time processor to ZU3EG products that have graphics processing capabilities (GPUs).

WebAmP R.D. Tool

Download Test Data

Design recommended by AMD

FULL POWER MANAGEMENT

POWER TREE MAPPING – FULL POWER MANAGEMENT

#	Rail	Seq	Power Component	Type	Upstream Rail	Vinput (V)	Vout (V)	Iout (A)	AnDAPT PMIC
1	VCC_PSINTLP	1	C200	Sync Buck	PVIN	12	0.85	0.7	ARD_X_ZUM_D1_IC1
2	VCC_PSAUX (VCC_PSAUX, VCC_PSADC)	2	C150	Async Buck	PVIN	12	1.8	0.5 + 0.010 + 0.035	ARD_X_ZUM_D1_IC1
3	VCC_PSPLL	3	C710	LDO	VCC_PSAUX	1.8	1.2	0.035	ARD_X_ZUM_D1_IC1
4	VCCO_PSIO	4	C150	Async Buck	PVIN	12	1.8 – 3.3	0.5	ARD_X_ZUM_D1_IC1
5	VCC_PSINTFP (VCC_PSINTFP, VCC_PSINTFP_DDR)	5	C200	Sync Buck	PVIN	12	0.85	1.4	ARD_X_ZUM_D1_IC1
6	VCC_PSDDR_PLL	6	C750	Load Switch	VCC_PSAUX	1.8	1.8	0.010	ARD_X_ZUM_D1_IC1
7	VCC0_PSDDR (VCC0_PSDDR, DDR_VDDQ/ VDD)	7	C200	Sync Buck	PVIN	12	1.1 – 1.5	3	ARD_X_ZUM_D1_IC1
8	VCCINT (VCCINT, VCCBRAM, VCCINT_IO)	8	C200	Sync Buck	PVIN	12	0.85/0.72	1 – 3.5	ARD_X_ZUM_D1_IC1
9	VCCBRAM	8	C200	Sync Buck	PVIN	12	0.85	1	ARD_X_ZUM_D1_IC1
10	VCCAUX (VCCAUX, VCCAUX_IO, VCCADC)	9	C200	Sync Buck	PVIN	12	1.8	0.4	ARD_X_ZUM_D1_IC1

ANDAPT SOLUTION – FULL POWER MANAGEMENT

DESIGN VIEW IC1

THERMAL VIEW IC1

DESIGN VIEW IC2

THERMAL VIEW IC2

TEST DATA

Download Design